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AVRILOS Project Information


This is the AVRILOS project ("avrilos"). An Embedded System simple Operating System Framework that allows rapid development of applications build for AVR family but can be ported to other architectures easily enough. System is Round-Robin Co-operative multitasking. Supports: UART, SysTick Timer, ADC, SPI, EEPROM, PWM. Also supports: Xilinx FPGA configuration, FPGA SSI interface, smart card reader etc. Tested partially (different modules in each case) on ATMega163/16/32/323/8. Additionally tools for converting FPGA bitstreams to C table are provided.

AVRILOS Timeline:

2010 Nov: AVRILOS went open source on CodeProject.
2010 Dec: Prize winner in Competition "Hardware and Device Programming Competition" (Third Prize level), CodeProject.
2011 May: Released the FPGA flow for bitstream to C ROM table conversion.
2011 May: Released FPGA integration with AVRILOS. Demonstrated an FPGA based 8-channel R/C Servo controller.
2011 May: This project was registered on
2011 Nov, V1.23: Did some bug fixes and timer enhancements.
2012 Jan, V1.24: Fixed a critical bug of an enhancement on SysTick.


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Source code for this project may be available as: Downloads
SCM repositories used, as accessible from the: project develop page.
Changesets can be found at: Mercurial Changesets